Hi everyone,
I was wondering how other teachers are interpreting this statement in the N5 course specification:
Basic computer architecture: processor, memory, buses, interfaces
At Higher the only difference is the absence of the word ‘Basic’. We have started to put a draft timeline together and at N5 level we have planned to look at:
CPU – ALU, Control Unit, Registers
Memory – RAM, ROM, Cache (brief)
Bus – Data Bus, Address Bus, Control Lines (State)
Interfaces – Examples of (USB, Firewire etc), Status Signals, Data Format Conversion
This means that we would leave the following until the new Higher:
Fetch/Execute Read and Write (Steps in Order with ref to Control lines)
Maximum addressable memory
Cache – More depth
Interfaces – Voltage Conversion, Protocol Conversion, Buffering, Relationship with OS (I/O, Drivers etc)
Time looks tight for us because of the nature of our timetable. Do you think this seems like a sensible approach? Is anything missing?
Thanks
Joe
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